The present invention relates to technology mapping techniques for programmable logic integrated circuits, and more particularly, to techniques for applying local searching to technology mapping.
Programmable logic integrated circuits typically include thousands of programmable logic elements that use logic gates and/or a lookup tables to perform logic operations. Programmable logic integrated circuits can also have a number of functional blocks adapted to perform specific logic operations. By configuring the combination of logic elements and functional blocks, a programmable logic integrated circuit (IC) can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable logic IC starts with an extraction phase, followed by a logic synthesis phase, and a placement and routing phase. The extraction phase produces a set of logic gates implementing the user design. A user design for a programmable IC is typically expressed as a netlist in a hardware description language such as verilog or VHDL.
In the logic synthesis phase, the set of logic gates is minimized and restructured, and then finally transformed into elements that correspond to portions of the programmable IC. The logic synthesis phase includes a technology mapping phase, during which simple logic gates in the netlist are replaced with lookup tables (LUTs) without changing the functionality of the netlist.
Typically, the technology mapping phase optimizes the netlist to minimize the usage of hardware in the programmable IC hardware (e.g., the number of logic elements or functional blocks). By minimizing the usage of programmable IC hardware, referred to generally as area, the user design can be implemented using the simplest and presumably least expensive programmable IC. However, minimizing the area of a user design tends to create data paths that pass through a large number of logic cells and/or functional blocks. This in turn increases the delay on data paths and decreases the maximum operating speed of the user design.
Alternatively, some technology mapping tools optimize strictly for maximum operating speed. Unfortunately, these methods substantially increase the area requirements for a user design. As a result, the cost to implement the speed-optimized user design also increases. Furthermore, many speed optimization techniques increase area so much that the performance improvements gained from using additional programmable IC hardware are negated by the additional routing delays introduced by the increased area of the design. Thus, the actual speed increase from these tools often falls short of theoretical projections.
A balanced technology mapping tool combines speed and area optimizations by initially using speed mapping to generate a mapping for a netlist, and then adjusting this mapping for the 10% of the logic gates that are on paths having the longest delays. The balanced mapping tool applies area mapping to the remaining 90% of the logic gates in the netlist.
It would however be desirable to provide more flexible techniques for technology mapping that improve the area and the speed of a user design.